NOTE: DOCUMENTATION NEEDS UPDATING.

• Overview
• Directory Structure
• Dependencies
• Setup
  • Install Dependencies
  • Compile the Verilog Modules
  • Run the ROS Node
  • Automate the Process
• Usage
• Detailed Descriptions
  • rosnode.py
  • tpu.py
  • uart_comm.v
  • top_L.v
  • cpu.v
  • fpga.v
  • main.py
  • mortymb.py
• Appendix
  • Power and Ground Connections
  • Helper Function
  • Components
  • Connections
  • Decoupling Capacitors
  • GPIO Integration Plans
• Conclusion

This project implements a bipedal humanoid control system using a Physics-Informed Neural Network (PINN) and Reinforcement Learning (RL) for stability and manipulation tasks. The system integrates with ROS for real-time control and utilizes FPGA for hardware acceleration. Central to this system is the Dreamer algorithm, which provides high-level planning and decision-making, ensuring optimal performance in complex, dynamic environments.

• rosnode.py: Located in /mother/Software_Firmware/rosnode.py. This ROS node script is responsible for subscribing to sensor data topics, processing data, and publishing control signals.
• tpu.py: Located in the root directory, this script handles the Physics-Informed Neural Network (PINN), Reinforcement Learning (RL), Dreamer integration, communication with FPGA, and optimization using CasADi.
• uart_comm.v: Verilog module for UART communication with FPGA.
• top_L.v: Top-level Verilog module integrating all components.
• cpu.v: Verilog module for the CPU.
• fpga.v: Verilog module for the FPGA.
• main.py: Script to compile the Verilog modules, run the ROS node, start systemd services, and execute MicroPython scripts for control interfacing.
• mortymb.py: Defines the electronic components and connections for the robotâ��s motherboard using skidl.
• README.md: This file.

• ROS (Robot Operating System)
• Python 3.x
• TensorFlow
• CasADi
• scikit-learn
• iverilog (for Verilog compilation)
• KiCad (for electronic design)

Ensure all dependencies are installed using the following commands:

sudo apt-get install ros-humble-desktop-full
sudo apt-get install iverilog kicad
pip install tensorflow casadi scikit-learn

Compile the Verilog modules using iverilog and vvp:

iverilog -o uart_comm uart_comm.v
iverilog -o top_L top_L.v
iverilog -o cpu cpu.v
iverilog -o fpga fpga.v
vvp uart_comm
vvp top_L
vvp cpu
vvp fpga

Start the ROS node that runs the system:

rosrun bipedal_control rosnode.py

Alternatively, use the main.py script to compile the Verilog modules and run the ROS node:

python main.py

The system is designed to control a bipedal humanoid robot. It subscribes to ROS topics for sensor data, including joint states and forces, and publishes control signals to actuate the robot's movements. The PINN model, enhanced by the Dreamer algorithm, ensures stability, manipulation capabilities, and high-level planning, while the RL agent optimizes control strategies over time. The Dreamer algorithm is a critical component, offering foresight and strategy to navigate complex scenarios.

• Location: /mother/Software_Firmware/rosnode.py
• Purpose: Acts as the interface between ROS and the TPU module. It handles the collection, normalization, and transmission of sensor data to the TPU, and receives optimized control signals for robot actuation.
• Functionality:
  • Initializes the ROS node and subscribers for sensor data.
  • Normalizes sensor data using StandardScaler.
  • Sends normalized data to the TPU module over a TCP/IP connection.
  • Publishes the received control signals back to ROS for robot actuation.
  • Facilitates communication with Dreamer-enhanced TPU processing, ensuring the control signals are based on strategic, high-level plans generated by the Dreamer algorithm.

• Location: Root directory
• Purpose: Implements the main control algorithms using the Physics-Informed Neural Network (PINN) and Reinforcement Learning (RL). It also handles communication with the FPGA and Dreamer-based optimization.
• Functionality:
  • PINN Architecture: A deep neural network designed for stability and manipulation tasks.
  • Reinforcement Learning: An RL agent to optimize control strategies over time, integrated with the Dreamer model for high-level planning.
  • Dreamer Integration: Provides strategic foresight and planning, ensuring the control strategies are optimized not only for immediate stability but also for future goals and challenges.
  • Optimization: Uses CasADi to define and solve optimization problems for control signals, influenced by Dreamerâ��s planning.
  • Communication: Establishes serial communication with the FPGA and TCP/IP communication with the ROS node.

• Purpose: Defines the Verilog module for UART communication with the FPGA.
• Functionality:
  • Implements UART communication protocols.
  • Facilitates data exchange between the FPGA and other components.

• Purpose: Defines the top-level Verilog module integrating the CPU, FPGA, and UART modules.
• Functionality:
  • Connects the CPU, FPGA, and UART communication.
  • Manages data flow between components.

• Purpose: Defines the Verilog module for the CPU.
• Functionality:
  • Implements the CPU operations and interfaces with the UART and FPGA modules.

• Purpose: Defines the Verilog module for the FPGA.
• Functionality:
  • Implements FPGA operations and interfaces with the CPU and UART modules.

• Purpose: Automates the compilation of Verilog modules, execution of the ROS node, starts systemd services, and runs MicroPython scripts for centralized control interfacing.
• Functionality:
  • Compiles the Verilog modules using iverilog and vvp.
  • Runs the rosnode.py script using rosrun.
  • Starts specified systemd services using systemctl.
  • Executes a specified MicroPython script for centralized control interfacing.
  • Orchestrates the integration of the Dreamer algorithm into the system, ensuring that high-level planning and strategic foresight are central to the control and operation of the robot.

• Purpose: Defines and connects the electronic components of the robot’s motherboard using skidl for electronic design automation.
• Functionality:
  • Project Structure: Creates a standard KiCad project structure with directories for schematic files, footprints, symbols, 3D models, and output files (Gerber, BOM, Netlist).
  • Component Definition and Connection: Defines components such as the NXP i.MX 8M Mini Quad, Xilinx Zynq MPSoC, and others, and establishes power and data connections between them.
  • File Generation: Generates netlist, BOM, Gerber files, and exports these in the appropriate formats.
  • Library Integration: Downloads and integrates component libraries (footprints and symbols) from provided URLs.
  • Git Integration: Initializes a Git repository and commits the initial project structure.
  • Customization: Configures project settings and user preferences for the KiCad project.
  • Dreamer Integration Consideration: The design is structured to support the complex data flows and computational demands required by the Dreamer-enhanced control system.

will be revised

• GND: Ground.
• i.MX8M_VCC: Power supply for the NXP i.MX 8M Mini Quad.
• ZYNQ_VCC: Power supply for the Xilinx Zynq MPSoC.
• SSD_VCC: Power supply for the one terabyte external SSD.
• IMU_VCC: Power supply for the Bosch BNO080.
• WIFI_BT_VCC: Power supply for the Intel 9260NGW.
• TPU_VCC: Power supply for the Google Coral Edge TPU.
• DRV_VCC: Power supply for the TI DRV8432.
• USB_VCC: Power supply for USB ports.
• ETH_VCC: Power supply for the Ethernet controller and port.
• UART_VCC: Power supply for UART communication module.
• PMIC_VCC: Power supply from the Power Management IC.
• CLOCK_VCC: Power supply for the Crystal Oscillator.
• FLASH_VCC: Power supply for Flash memory.

• add_decoupling_caps(part, pin_name, gnd, num_caps=2):
  • Adds decoupling capacitors to a specified part and pin.
  • Decoupling capacitors help stabilize the power supply to the components.

The script defines the following components:

• U1: NXP i.MX 8M Mini Quad, BGA-400.
• U2: Xilinx Zynq MPSoC, BGA-484.
• U3: Micron LPDDR4 4GB, BGA-178.
• U4: Samsung eMMC 128GB, BGA-153.
• U5: Bosch BNO080, LGA-28.
• U6: Intel 9260NGW, M.2 (2230).
• U7: Google Coral Edge TPU, M.2 Key E.
• U8: TI DRV8432, HTSSOP-36.
• U9: TI TPS65988, VQFN-48.
• U10: Analog ADP5054, LFCSP-32.
• C1-C20: 100nF Capacitors, 0805.
• L1: Inductor (Power Filter), 0603.
• C21-C22: 22uF Capacitors, 0805.
• R1-R2: 10kΩ Resistors, 0603.
• U11: Crystal Oscillator, 4-pin.
• D1: Schottky Diode, SOD-123.
• U12: Level Shifter, TSSOP-8.
• Q1: N-Channel MOSFET, SOT-23.
• C23-C24: 100uF Capacitors, 1210.
• R3-R4: 47Ω Resistors, 0603.
• U13: RTC (Real-Time Clock), SOIC-8.
• U14: EEPROM, SOIC-8.
• J1: Main Power Connector, Through-hole.
• J2: Programming Header, Through-hole.
• J3: UART Header, Through-hole.

The mortymb.py script establishes connections for power and data lines between components:

• Power and Ground Connections:

  • Connects each component’s power and ground pins to the respective power nets.
  • Example: vcc += zynq['VCC'].

• i.MX 8M Mini Quad and RAM:

  • Connects address and data lines between the i.MX 8M Mini Quad and LPDDR4 RAM modules.
  • Example: imx['AD0', 'AD1', ...] += ram['DQ0', 'DQ1', ...].

• FPGA:

  • Connects FPGA power and ground pins.
  • Example: vcc += fpga['VCC'].

• UART Communication:

  • Connects UART communication lines between the i.MX 8M Mini Quad, Zynq MPSoC, and UART module.
  • Example: imx['GPIO1'] += uart['T1IN'].

• i.MX 8M Mini Quad to USB:

  • Connects data lines between the i.MX 8M Mini Quad and USB controller.
  • Example: imx['GPIO21'] += usb['DP'].

• i.MX 8M Mini Quad to Ethernet:

  • Connects data lines between the i.MX 8M Mini Quad and Ethernet controller.
  • Example: imx['GPIO0'] += eth['TXEN'].

• PMIC:

  • Connects the PMIC to provide regulated power to various components.
  • Example: pmic['OUT1'] += imx['VCC'].

Decoupling capacitors are essential for stabilizing the power supply to each component by filtering out noise and preventing voltage drops, which can be caused by sudden changes in current draw. The following guidelines are implemented in the mortymb.py script to add decoupling capacitors for each major component:

• Placement: Decoupling capacitors are placed as close as possible to the power pins of each component to minimize inductive effects in the power supply traces.
• Capacitor Values:
  • 0.1 µF Capacitors: Used for high-frequency noise filtering. These are the most common decoupling capacitors and are placed across the power supply pins of every IC.
  • 10 µF Capacitors: Used for lower frequency filtering and provide bulk capacitance to support power demands during sudden changes in load.
• Pin Connections:
  • Each power pin of a component is connected to both a 0.1 µF and a 10 µF capacitor.
  • The capacitors are connected between the power pin and ground.

Example code from mortymb.py to add decoupling capacitors:

from skidl import Part, Net
'''
if im even using skidl
at this point... *needing outside footprints 
and kicad 8.🙄
'''

def add_decoupling_caps(part, pin_name, gnd, num_caps=2):
    for _ in range(num_caps):
        cap = Part('Device', 'C', value='0.1uF')
        cap[1] += part[pin_name]
        cap[2] += gnd
    bulk_cap = Part('Device', 'C', value='10uF')
    bulk_cap[1] += part[pin_name]
    bulk_cap[2] += gnd

# Example usage:
vcc = Net('VCC')
gnd = Net('GND')
imx = Part('Processor', 'iMX8M', footprint='BGA-400')
add_decoupling_caps(imx, 'VCC', gnd)

The current design includes GPIO (General Purpose Input/Output) integration for enhanced sensor interfacing and integral control capabilities, making the system versatile for future expansions and customizations.

This project aims to provide a comprehensive system for controlling a bipedal humanoid robot and integrating advanced hardware with sophisticated software algorithm so the robot can achieve stable and optimized performance in real-time environments.