Targets N25Q128 memory, adaptable to other ones. Can read memory chip ID, enable quad SPI mode, disable write protection, erase sectors, do bulk erase, program pages and poll the status register.

top.v can be used to implement a minimal test design for a Xilinx FPGA (tested on Artix); STARTUPE2 primitive is used to talk to the boot memory of the FPGA. top.xdc are the constraints to use together. Configured to run from 100 MHz external clock converting it to 40 MHz for SPI; indicates the test progress using 2 LEDs. Use impl.sh to run the implementation with Vivado.

testbench.v wraps top.v for a simulation with the Verilog model of the memory. sim_iverilog.sh runs the simulation with Icarus Verilog; sim_vivado.sh runs the Xilinx Vivado simulator.

• use get_mem_model.sh to download and prepare memory model files for N25Qxxx; N25Qxxx.v will be patched
• Xilinx primitives Verilog model files from Vivado (see sim_iverilog.sh)

• the 256-byte wide data interface is definitely inoptimal for implementation (though it works) and should be replaced with something more reasonable
• add other memory models